Job Details

Job Description

As a member of Intel's CPU development team, you will have a front seat in designing the latest core IP to power cutting edge compute processors across client, server, IOTG and AI. We innovate state of the art microprocessor architecture on the most advanced and latest process technologies with a focus on power efficiency. Our core designs are present in nearly all segments of Intel's compute roadmap.

Job Responsibilities

• Perform physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conduct all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyze results and make recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
• Possess CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Work intimately with industry EDA vendors to build and enhance tool capabilities to design a high‑speed, low‑power synthesizable CPU.
• Optimize CPU design to improve product‑level parameters such as power, frequency, and area.
• Participate in the development and improvement of physical design methodologies and flow automation.

Qualifications

• Minimum Qualifications: Bachelors in Computer Engineering or Electrical Engineering with 3+ years of relevant work experience or M.S. in Computer Engineering or Electrical Engineering (or higher degree) with 2+ years of relevant work experience.
• 2+ years of experience in integrated circuit design tools (e.g., Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure; PV convergence; chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, noise and electro‑migration checks; scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby); synthesis of a digital logic block integrated into a large SoC or IP.

Preferred Qualifications

• Physical design best practices concerning floor‑planning, routing techniques, clock distribution.
• Static Timing Analysis, Noise analysis, and reliability verification techniques.
• RTL to GDS methodologies and formal equivalence.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Business Group

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry‑leading products today while also defining the next generation of computing experiences.

Work Model

This role will require an on‑site presence.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $122,440.00 - 232,190.00 USD.